Invention Grant
- Patent Title: Closed cell configuration to increase channel density for sub-micron planar semiconductor power device
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Application No.: US11473938Application Date: 2006-06-23
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Publication No.: US07956384B2Publication Date: 2011-06-07
- Inventor: Shekar Mallikararjunaswamy
- Applicant: Shekar Mallikararjunaswamy
- Applicant Address: BM
- Assignee: Alpha & Omega Semiconductor Ltd.
- Current Assignee: Alpha & Omega Semiconductor Ltd.
- Current Assignee Address: BM
- Agent Bo-In Lin
- Main IPC: H01L27/118
- IPC: H01L27/118 ; H01L23/52 ; H01L27/088 ; H01L27/105

Abstract:
A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.
Public/Granted literature
- US20070295996A1 Closed cell configuration to increase channel density for sub-micron planar semiconductor power device Public/Granted day:2007-12-27
Information query
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