A vertical pillar semiconductor device includes a substrate, a single crystalline semiconductor pattern, a gate insulation layer structure and a gate electrode. The substrate may include a first impurity region. The single crystalline semiconductor pattern may be on the first impurity region. The single crystalline semiconductor pattern has a pillar shape substantially perpendicular to the substrate. A second impurity region may be formed in an upper portion of the single crystalline semiconductor pattern. The gate insulation layer structure may include a charge storage pattern, the gate insulation layer structure on a sidewall of the single crystalline semiconductor pattern. The gate electrode may be formed on the gate insulation layer structure and opposite the sidewall of the single crystalline semiconductor pattern. The gate electrode has an upper face substantially lower than that of the single crystalline semiconductor pattern.