Invention Grant
- Patent Title: Method of reducing stacking faults through annealing
- Patent Title (中): 通过退火减少堆垛层错的方法
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Application No.: US12839588Application Date: 2010-07-20
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Publication No.: US07956417B2Publication Date: 2011-06-07
- Inventor: Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
- Applicant: Yun-Yu Wang , Christopher D. Sheraw , Anthony G. Domenicucci , Linda Black , Judson R. Holt , David M. Fried
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Ian D. MacKinnon
- Main IPC: H01L27/12
- IPC: H01L27/12

Abstract:
Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.
Public/Granted literature
- US20100283089A1 METHOD OF REDUCING STACKING FAULTS THROUGH ANNEALING Public/Granted day:2010-11-11
Information query
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