Invention Grant
US07956461B2 Semiconductor apparatus including semiconductor chip with stress material selectively provided in region of wiring layer
失效
包括具有应力材料的半导体芯片的半导体装置选择性地设置在布线层的区域中
- Patent Title: Semiconductor apparatus including semiconductor chip with stress material selectively provided in region of wiring layer
- Patent Title (中): 包括具有应力材料的半导体芯片的半导体装置选择性地设置在布线层的区域中
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Application No.: US12230684Application Date: 2008-09-03
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Publication No.: US07956461B2Publication Date: 2011-06-07
- Inventor: Takayuki Iwaki
- Applicant: Takayuki Iwaki
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2007/229682 20070905
- Main IPC: H01L23/482
- IPC: H01L23/482

Abstract:
In order to solve a problem of occurrence of delamination of interlayer film due to occurrence of a crack in an LSI wiring layer in a UBM lower layer immediately under a solder bump in an outer periphery of an LSI chip, a semiconductor apparatus of the present invention includes a stress boundary between compressive stress and tensile stress in an LSI wiring layer of a bump lower layer and in order to alleviate the stress present in the bump lower layer tensile stress material is arranged on a compressive stress side or compressive stress material is arranged on a tensile stress side with a stress boundary of the LSI wiring layer as a boundary.
Public/Granted literature
- US20090057893A1 Semiconductor apparatus Public/Granted day:2009-03-05
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