Invention Grant
- Patent Title: Impedance adjusting circuit
- Patent Title (中): 阻抗调节电路
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Application No.: US12651771Application Date: 2010-01-04
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Publication No.: US07956638B2Publication Date: 2011-06-07
- Inventor: Yoichi Iizuka , Masayasu Komyo
- Applicant: Yoichi Iizuka , Masayasu Komyo
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Foley & Lardner LLP
- Priority: JP2009-012920 20090123
- Main IPC: H03K17/16
- IPC: H03K17/16

Abstract:
An impedance adjusting circuit that includes an external terminal to which an external resistor is connected, a first transistor array of a first conductivity type that is connected in parallel between the external terminal and a first power supply terminal and changes a voltage of the external terminal by adjusting an impedance in response to a first control signal, a second transistor array of a second conductivity type that is connected in parallel between the external terminal and a second power supply terminal and changes the voltage of the external terminal by adjusting the impedance in response to a second control signal, and a control circuit that specifies the first control signal according to a comparison result between the voltage of the external terminal and a reference voltage and specifies the second control signal in a different period from a period to specify the first control signal.
Public/Granted literature
- US20100188116A1 IMPEDANCE ADJUSTING CIRCUIT Public/Granted day:2010-07-29
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