Invention Grant
- Patent Title: Buffer circuit and control method thereof
- Patent Title (中): 缓冲电路及其控制方法
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Application No.: US12029778Application Date: 2008-02-12
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Publication No.: US07956646B2Publication Date: 2011-06-07
- Inventor: Hiromitsu Osawa
- Applicant: Hiromitsu Osawa
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Arent Fox LLP
- Priority: JP2007-038939 20070220
- Main IPC: H03K19/094
- IPC: H03K19/094 ; H03K19/20 ; H03K5/12

Abstract:
The present disclosure has been worked out to provide a buffer circuit and a control method thereof capable of controlling the timing at which the output switching element is changed from an OFF state to an ON state, and preventing the output characteristic from becoming unstable. The buffer circuit includes: a driving portion 20 driving output switching elements M1 and M2; a detecting portion 30 detecting that the voltage values of control terminals of the output switching elements M1 and M2 have exceeded the threshold voltage value; an auxiliary driving portion 40 being connected to the driving portion 20 and changing driving capability of the output switching elements M1 and M2 in accordance with the result of detection by the detecting portion 30.
Public/Granted literature
- US20080197892A1 BUFFER CIRCUIT AND CONTROL METHOD THEREOF Public/Granted day:2008-08-21
Information query
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