An integrated circuit includes a memory array including a plurality of memory cells, the memory cells include a core storage element having at least a first storage node (S) and a complementary second storage node (S-bar), and a first pass gate coupled to the first storage node (S). A single bitline (BL) is coupled to a node in a source drain path of the first pass gate. The BL is for Reading data from and Writing data to the first storage node (S). A buffer circuit includes a second pass gate and a driver transistor, wherein the second pass gate is coupled between the driver transistor and the source drain path of the first pass gate. A gate of the driver transistor is coupled to the second storage node (S-bar). At least one wordline (WL) is coupled to the first pass gate and the second pass gate.