Invention Grant
US07957183B2 Single bit line SMT MRAM array architecture and the programming method
有权
单位SMT MRAM阵列架构和编程方法
- Patent Title: Single bit line SMT MRAM array architecture and the programming method
- Patent Title (中): 单位SMT MRAM阵列架构和编程方法
-
Application No.: US12387537Application Date: 2009-05-04
-
Publication No.: US07957183B2Publication Date: 2011-06-07
- Inventor: Hsu Kai Yang
- Applicant: Hsu Kai Yang
- Applicant Address: US CA Milpitas
- Assignee: MagIC Technologies, Inc.
- Current Assignee: MagIC Technologies, Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman; Billy Knowles
- Main IPC: G11C11/14
- IPC: G11C11/14

Abstract:
An SMT MRAM device includes a plurality of SMT MRAM cells arranged in an array of rows and columns. Single bit lines connect the columns of the SMT MRAM cells for receiving an in-phase data signal. Source lines connect pairs of rows of the SMT MRAM cells for receiving an out-of-phase data signal. Out-of-phase switching devices are connected to the source lines for selectively transferring the out-of-phase signal to the at least one source lines. Column select transistors are connected to the single bit lines for transferring an in-phase data signal to a selected column of the SMT MRAM cells. A precharge circuit selectively charges or discharges the single bit lines. Ground switching devices selectively connect to the source lines to a ground reference voltage source. A method for programming a selected SMT MRAM cell within a provided SMT MRAM device is described.
Public/Granted literature
- US20100277974A1 Single bit line SMT MRAM array architecture and the programming method Public/Granted day:2010-11-04
Information query