Invention Grant
US07958182B2 Providing full hardware support of collective operations in a multi-tiered full-graph interconnect architecture 失效
在多层全图互连架构中提供集体操作的完整硬件支持

Providing full hardware support of collective operations in a multi-tiered full-graph interconnect architecture
Abstract:
A mechanism is provided for performing collective operations. In hardware of a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In hardware of the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output.
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