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US07958404B2 Enabling resynchronization of a logic analyzer 失效
启用逻辑分析仪的重新同步

Enabling resynchronization of a logic analyzer
Abstract:
In one embodiment, a state machine may enable retraining of a link, where the state machine is to be initiated responsive to an external input received from a logic analyzer coupled to the link or a periodic timer. Such external input may indicate that the logic analyzer has lost synchronization with respect to link communications, and the retraining thus enables the logic analyzer to regain resynchronization. Other embodiments are described and claimed.
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