Invention Grant
- Patent Title: Enabling resynchronization of a logic analyzer
- Patent Title (中): 启用逻辑分析仪的重新同步
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Application No.: US12414733Application Date: 2009-03-31
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Publication No.: US07958404B2Publication Date: 2011-06-07
- Inventor: Keith Drescher , Debendra Das Sharma , David Sams , Richard Glass
- Applicant: Keith Drescher , Debendra Das Sharma , David Sams , Richard Glass
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
In one embodiment, a state machine may enable retraining of a link, where the state machine is to be initiated responsive to an external input received from a logic analyzer coupled to the link or a periodic timer. Such external input may indicate that the logic analyzer has lost synchronization with respect to link communications, and the retraining thus enables the logic analyzer to regain resynchronization. Other embodiments are described and claimed.
Public/Granted literature
- US20100251001A1 Enabling Resynchronization Of A Logic Analyzer Public/Granted day:2010-09-30
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