A memory chip includes a receiver, a clock phase shifter, an error detector, and a controller. The receiver receives a test signal having a plurality of random data bits. The clock phase shifter shifts the phase of a clock signal to one of first through nth phases (n is a natural number). The controller controls the clock phase shifter to sequentially increase the phase of the clock signal from the first phase when the error detector determines the data bit sampled in synchronization with the clock signal has an erro has an error. The controller controls the clock phase shifter to sequentially decrease the phase of the clock signal from the nth phase when none of the plurality of data bits sampled in synchronization with the clock signal having a kth phase (k is a natural number greater than 1 and smaller than n−1) have an error.