Invention Grant
- Patent Title: Single-pass, concurrent-validation methods for generating test patterns for sequential circuits
- Patent Title (中): 用于生成连续电路测试模式的单通,并发验证方法
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Application No.: US11893683Application Date: 2007-08-16
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Publication No.: US07958421B2Publication Date: 2011-06-07
- Inventor: Delmas R. Buckley, Jr.
- Applicant: Delmas R. Buckley, Jr.
- Applicant Address: US CA Livermore
- Assignee: Yardstick Research, LLC
- Current Assignee: Yardstick Research, LLC
- Current Assignee Address: US CA Livermore
- Agent Robert Buckley
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G06F11/00

Abstract:
A single-pass, concurrent validation method for generating test pattern sequences for sequential circuits maps fault objects arriving at circuit next-state lines into good next-state fault objects, and passes these mapped results to a next time-frame by placing the good next-state fault objects on present-state lines corresponding to the next-state lines at which to fault objects arrived. Path-enabling functions created during an initial time-frame are reused for all subsequent time-frames, permitting a fault-propagation size and a path-enabling function size to be bounded by a function size established during the initial time-frame. A valid test pattern sequence is found when a primary output line has a good output level that is a complement of a faulty output level for the line. In one embodiment, the determination and comparison of output levels is carried out concurrently.
Public/Granted literature
- US20090049354A1 Single-pass, concurrent-validation methods for generating test patterns for sequential circuits Public/Granted day:2009-02-19
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