Invention Grant
US07958477B2 Structure, failure analysis tool and method of determining white bump location using failure analysis tool
有权
使用故障分析工具确定白色凹凸位置的结构，故障分析工具和方法
- Patent Title: Structure, failure analysis tool and method of determining white bump location using failure analysis tool
- Patent Title (中): 使用故障分析工具确定白色凹凸位置的结构，故障分析工具和方法
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Application No.: US12046608Application Date: 2008-03-12
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Publication No.: US07958477B2Publication Date: 2011-06-07
- Inventor: Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
- Applicant: Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran & Cole, P.C.
- Agent Anthony Canale
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455
Abstract:
A failure analysis tool, a method of using the tool and a design structure for designing a mask for protecting a critical area of wiring failure in a semiconductor chip during packaging is provided. The failure analysis tool includes a computer infrastructure operable to determine a risk area for wiring layer failure during solder bump formation by determining a distance from a center of a chip to a location for a solder bump processing and identifying an area at an edge of the location for the solder bump processes at a predetermined distance and greater from the center of the chip.
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