Structure and method to integrate dual silicide with dual stress liner to improve CMOS performance

Invention Grant

US07960223B2 Structure and method to integrate dual silicide with dual stress liner to improve CMOS performance 失效

Title translation: 将双重硅化物与双重应力衬片集成在一起的结构和方法可提高CMOS性能

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Patent Title: Structure and method to integrate dual silicide with dual stress liner to improve CMOS performance
Patent Title (中): 将双重硅化物与双重应力衬片集成在一起的结构和方法可提高CMOS性能
Application No.: US12139764

Application Date: 2008-06-16
Publication No.: US07960223B2

Publication Date: 2011-06-14
Inventor: Xiangdong Chen , Haining S. Yang
Applicant: Xiangdong Chen , Haining S. Yang
Applicant Address: US NY Armonk
Assignee: International Business Machines Corporation
Current Assignee: International Business Machines Corporation
Current Assignee Address: US NY Armonk
Agency: Scully, Scott, Murphy & Presser, P.C.
Agent H. Daniel Schnurmann
Main IPC: H01L21/8238
IPC: H01L21/8238

Structure and method to integrate dual silicide with dual stress liner to improve CMOS performance

Abstract:

The present invention provides a semiconducting device including a substrate including a semiconducting surface having an n-type device in a first device region and a p-type device in a second device region, the n-type device including a first gate structure present overlying a portion of the semiconducting surface in the first device region including a first work function metal semiconductor alloy in the semiconducting surface adjacent to the portion of the semiconducting surface underlying the gate structure, and a first type strain inducing layer present overlying the first device region; and a p-type device including a second gate structure present overlying a portion of the semiconducting surface in the second device region including a second work function metal semiconductor alloy in the semiconducting surface adjacent to the portion of the semiconducting surface underlying the gate structure, and a second type strain inducing layer present overlying the second device region.

Abstract(Chinese):

本发明提供了一种半导体器件，其包括：衬底，其包括在第一器件区域中具有n型器件的半导体表面和在第二器件区域中的p型器件，所述n型器件包括第一栅极结构，所述第一器件区域中的所述半导体表面的部分包括与所述栅极结构下方的所述半导体表面的部分相邻的所述半导体表面中的第一功函数金属半导体合金，以及存在于所述第一器件区域上方的第一类型应变诱导层; 以及包括第二栅极结构的p型器件，所述第二栅极结构覆盖所述第二器件区域中的所述半导体表面的一部分，所述第二栅极结构包括与所述栅极结构的所述半导体表面的所述部分相邻的所述半导体表面中的第二功函数金属半导体合金，存在覆盖在第二器件区域上的第二类型应变诱导层。

Public/Granted literature

US20090309164A1 STRUCTURE AND METHOD TO INTEGRATE DUAL SILICIDE WITH DUAL STRESS LINER TO IMPROVE CMOS PERFORMANCE Public/Granted day:2009-12-17

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS