Invention Grant
US07960272B2 Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
有权
用于制造用于芯片级封装的热适应性半导体芯片布线结构的方法
- Patent Title: Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
- Patent Title (中): 用于制造用于芯片级封装的热适应性半导体芯片布线结构的方法
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Application No.: US11761360Application Date: 2007-06-11
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Publication No.: US07960272B2Publication Date: 2011-06-14
- Inventor: Jin-Yuan Lee , Shih-Hsiung Lin
- Applicant: Jin-Yuan Lee , Shih-Hsiung Lin
- Applicant Address: TW Hsinchu
- Assignee: Megica Corporation
- Current Assignee: Megica Corporation
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.
Public/Granted literature
- US20070232053A1 METHOD FOR FABRICATING THERMAL COMPLIANT SEMICONDUCTOR CHIP WIRING STRUCTURE FOR CHIP SCALE PACKAGING Public/Granted day:2007-10-04
Information query
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