Invention Grant
- Patent Title: Method for reducing silicide defects in integrated circuits
- Patent Title (中): 降低集成电路中硅化物缺陷的方法
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Application No.: US12825325Application Date: 2010-06-28
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Publication No.: US07960283B2Publication Date: 2011-06-14
- Inventor: Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
- Applicant: Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
- Applicant Address: SG Singapore
- Assignee: Chartered Semiconductor Manufacturing, Ltd.
- Current Assignee: Chartered Semiconductor Manufacturing, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Horizon IP Pte Ltd
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/311

Abstract:
A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
Public/Granted literature
- US20100267236A1 METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS Public/Granted day:2010-10-21
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