Invention Grant
US07960765B2 Method and apparatus for providing an integrated circuit having p and n doped gates
有权
用于提供具有p和n掺杂栅极的集成电路的方法和装置
- Patent Title: Method and apparatus for providing an integrated circuit having p and n doped gates
- Patent Title (中): 用于提供具有p和n掺杂栅极的集成电路的方法和装置
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Application No.: US12467896Application Date: 2009-05-18
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Publication No.: US07960765B2Publication Date: 2011-06-14
- Inventor: Chandra Mouli , Kunal R. Parekh
- Applicant: Chandra Mouli , Kunal R. Parekh
- Applicant Address: KY George Town
- Assignee: Aptina Imaging Corporation
- Current Assignee: Aptina Imaging Corporation
- Current Assignee Address: KY George Town
- Main IPC: H01L31/062
- IPC: H01L31/062
Abstract:
A method and apparatus providing an integrated circuit having a plurality of gate stack structures having gate oxide layers with differing thicknesses and nitrogen concentrations and gate electrodes with differing conductivity types and active dopant concentrations.
Public/Granted literature
- US20090224299A1 METHOD AND APPARATUS FOR PROVIDING AN INTEGRATED CIRCUIT HAVING P AND N DOPED GATES Public/Granted day:2009-09-10
Information query
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