Invention Grant
- Patent Title: Tuning capacitance to enhance FET stack voltage withstand
- Patent Title (中): 调谐电容以增强FET堆叠电压耐受
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Application No.: US11796522Application Date: 2007-04-26
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Publication No.: US07960772B2Publication Date: 2011-06-14
- Inventor: Robert Mark Englekirk
- Applicant: Robert Mark Englekirk
- Applicant Address: US CA San Diego
- Assignee: Peregrine Semiconductor Corporation
- Current Assignee: Peregrine Semiconductor Corporation
- Current Assignee Address: US CA San Diego
- Agency: Jaquez & Associates
- Agent Martin J. Jaquez, Esq.; William C. Boling, Esq.
- Main IPC: H01L29/788
- IPC: H01L29/788

Abstract:
An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.
Public/Granted literature
- US20080265978A1 Tuning capacitance to enhance FET stack voltage withstand Public/Granted day:2008-10-30
Information query
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