Invention Grant
- Patent Title: Configuration of trenched semiconductor power device to reduce masked process
- Patent Title (中): 沟槽半导体功率器件的配置减少掩模过程
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Application No.: US12291365Application Date: 2008-11-07
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Publication No.: US07960787B2Publication Date: 2011-06-14
- Inventor: Fwa-Iuan Hshieh
- Applicant: Fwa-Iuan Hshieh
- Applicant Address: unknown British West Indies
- Assignee: Force-MOS Technology Corporation
- Current Assignee: Force-MOS Technology Corporation
- Current Assignee Address: unknown British West Indies
- Agent Bo-In Lin
- Main IPC: H01L29/78
- IPC: H01L29/78
Abstract:
A semiconductor power device formed on a semiconductor substrate of a first conductivity type wherein the semiconductor power device includes trench gates surrounded by body regions of a second conductivity type encompassing source regions of the first conductivity type therein. The semiconductor power device further includes trench contact structure having a plurality of trench contacts with trenches extended into the body regions for as source-body contacts and extended into the trench gates as gate contact. The semiconductor power device further includes a termination area wherein a plurality of the trench gate contacts are electrically connected to the source-body contacts.
Public/Granted literature
- US20100117145A1 Configuration of trenched semiconductor power device to reduce masked process Public/Granted day:2010-05-13
Information query
IPC分类:
