Invention Grant
- Patent Title: Self-aligned planar double-gate transistor structure
- Patent Title (中): 自对平面双栅晶体管结构
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Application No.: US12119765Application Date: 2008-05-13
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Publication No.: US07960790B2Publication Date: 2011-06-14
- Inventor: Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanararyan G. Hegde , Meikei Ieong , Erin Catherine Jones
- Applicant: Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanararyan G. Hegde , Meikei Ieong , Erin Catherine Jones
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Louis J. Percello, Esq.
- Main IPC: H01L27/01
- IPC: H01L27/01

Abstract:
A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.
Public/Granted literature
- US20080246090A1 SELF-ALIGNED PLANAR DOUBLE-GATE TRANSISTOR STRUCTURE Public/Granted day:2008-10-09
Information query
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