Invention Grant
US07960794B2 Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
有权
具有应变通道区域和集成应变CMOS流的非平面pMOS结构
- Patent Title: Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
- Patent Title (中): 具有应变通道区域和集成应变CMOS流的非平面pMOS结构
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Application No.: US12004706Application Date: 2007-12-20
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Publication No.: US07960794B2Publication Date: 2011-06-14
- Inventor: Brian S Doyle , Suman Datta , Been-Yih Jin , Nancy M Zelick , Robert Chau
- Applicant: Brian S Doyle , Suman Datta , Been-Yih Jin , Nancy M Zelick , Robert Chau
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L29/76
- IPC: H01L29/76

Abstract:
A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-y Gey layer, having the Ge content y higher than the Ge content x in the relaxed Si1-x Gex layer, is epitaxially grown on the fin. The Si1-y Gey layer covers the top and two sidewalls of the fin. The compressive stress in the Si1-y Gey layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.
Public/Granted literature
- US20080169512A1 Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow Public/Granted day:2008-07-17
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