Invention Grant
- Patent Title: Partially and fully silicided gate stacks
- Patent Title (中): 部分和完全硅化栅极堆叠
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Application No.: US12782388Application Date: 2010-05-18
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Publication No.: US07960795B2Publication Date: 2011-06-14
- Inventor: Leland Chang , Renee Tong Mo , Jeffrey W. Sleight
- Applicant: Leland Chang , Renee Tong Mo , Jeffrey W. Sleight
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Michael J. Chang, LLC
- Agent Vazken Alexanian
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L21/311

Abstract:
Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer.
Public/Granted literature
- US20100224940A1 Partially and Fully Silicided Gate Stacks Public/Granted day:2010-09-09
Information query
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