Invention Grant
- Patent Title: Integrated circuit arrangement with layer stack
- Patent Title (中): 集成电路布置与层叠
-
Application No.: US11438080Application Date: 2006-05-19
-
Publication No.: US07960832B2Publication Date: 2011-06-14
- Inventor: Heinrich Koerner
- Applicant: Heinrich Koerner
- Applicant Address: DE Munich
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Munich
- Agency: Brinks Hofer Gilson & Lione
- Priority: DE102005023122 20050519
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
An integrated circuit arrangement includes an electrically conductive conduction structure made from copper or a copper alloy. At a side wall of the conduction structure, there is a layer stack which includes at least three layers. Despite very thin layers in the layer stack, it is possible to achieve a high barrier action against copper diffusion combined with a high electrical conductivity, as is required for electrolytic deposition of copper using external current.
Public/Granted literature
- US20060267205A1 Integrated circuit arrangement with layer stack, and process Public/Granted day:2006-11-30
Information query
IPC分类: