Invention Grant
- Patent Title: Structure of high performance combo chip and processing method
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Application No.: US12269065Application Date: 2008-11-12
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Publication No.: US07960842B2Publication Date: 2011-06-14
- Inventor: Jin-Yuan Lee , Mou-Shiung Lin
- Applicant: Jin-Yuan Lee , Mou-Shiung Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Megica Corporation
- Current Assignee: Megica Corporation
- Current Assignee Address: TW Hsin-Chu
- Agency: McDermott Will & Emery, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump.
Public/Granted literature
- US20090057901A1 STRUCTURE OF HIGH PERFORMANCE COMBO CHIP AND PROCESSING METHOD Public/Granted day:2009-03-05
Information query
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