A variable delay circuit is designed to provided a wider range of delay time to a timing signal. The variable delay circuit includes a variable delay 50 which comprises a DA converter 51 which supplies current 51 based on delay setting data; a delay element 53 which imparts a delay amount Tpd to a prescribed signal and outputs the signal; and a bias circuit 52 which is connected such that the amount of current flown in the DA converter 51 and the amount of current flown in the delay element 53 become equal. The DA converter 51 allows the relationship between the delay setting data DATA and the current Id to be hyperbolic (inversely proportional). As a result, the relationship between the delay setting data DATA and the delay amount Tpd can be linearized, whereby the delay amount obtained by a single stage of the delay element can be increased.