A highly-integrated nonvolatile memory. A memory cell array where plural memory cells are arranged in matrix in row and column directions, plural first and second word lines, and plural bit lines are included. Each of the plural memory cells includes a first memory transistor and a second memory transistor which are connected in series. A gate electrode of the first memory transistor is connected to the first word line, a gate electrode of the second memory transistor is connected to the second word line, one of source and drain regions of the first memory transistor is connected to the first bit line, and one of source and drain regions of the second memory transistor is connected to the second bit line. Each of the first bit line and the second bit line is provided in common for memory cells in columns which are adjacent to each other.