Invention Grant
US07961832B2 All-digital symbol clock recovery loop for synchronous coherent receiver systems
有权
用于同步相干接收机系统的全数字符号时钟恢复回路
- Patent Title: All-digital symbol clock recovery loop for synchronous coherent receiver systems
- Patent Title (中): 用于同步相干接收机系统的全数字符号时钟恢复回路
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Application No.: US10225837Application Date: 2002-08-22
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Publication No.: US07961832B2Publication Date: 2011-06-14
- Inventor: Bernd Scheffler
- Applicant: Bernd Scheffler
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: H03D3/24
- IPC: H03D3/24
Abstract:
A symbol clock (16) associated with a symbol stream (5) in a synchronized communication receiver can be recovered by adjusting the phase of a symbol clock signal (12). The phase adjustment is accomplished by applying a digitally controlled delay (13) to the symbol clock signal based on a timing relationship between the symbol clock and symbol transitions (17) in the symbol stream.
Public/Granted literature
- US20030123571A1 All-digital symbol clock recovery loop for synchronous coherent receiver systems Public/Granted day:2003-07-03
Information query
IPC分类:
