Invention Grant
- Patent Title: Design structure for compensating for variances of a buried resistor in an integrated circuit
- Patent Title (中): 用于补偿集成电路中埋地电阻的方差的设计结构
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Application No.: US12135232Application Date: 2008-06-09
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Publication No.: US07962322B2Publication Date: 2011-06-14
- Inventor: Elie Awad , Mariette Awad , Kai Di Feng
- Applicant: Elie Awad , Mariette Awad , Kai Di Feng
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent David Cain
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L35/00
Abstract:
A design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a circuit that compensates for variances in the resistance of the buried resistor during operation of the integrated circuit using a waveform that is representative of the thermal characteristics of the buried resistor.
Public/Granted literature
- US20080234997A1 Design Structure for Compensating for Variances of a Buried Resistor in an Integrated Circuit Public/Granted day:2008-09-25
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