A memory controller has a control unit receiving a transfer data from a transmission circuit and executing a burst transfer of the transfer data to a reception circuit. The transmission circuit transmits a first data of a first bit length for a first burst times by a burst transmission. The amount of the transfer data is equal to a product of the first bit length and the first burst times. The reception circuit receives a second data of a second bit length for a second burst times by a burst reception. When the amount of the first data received by the control unit becomes equal to or more than a product of the second bit length and the second burst times, the control unit transfers the received first data as the second data to the reception circuit, regardless of the number of the first data received by the control unit.