Invention Grant
US07962819B2 Test mode soft reset circuitry and methods 有权
测试模式软复位电路和方法

Test mode soft reset circuitry and methods
Abstract:
An integrated circuit chip includes a scan-in pin, a scan clock pin, and a test controller. The scan-in pin and the scan clock pin receive a test program for the type of test mode and a soft-reset pattern. A state machine is configured to direct sampling of a scan clock waveform provided through the scan clock pin as dictated by transitions of a scan-in waveform provided through the scan-in pin. The state machine identifies a bit match from the sampled scan clock waveform upon executing the soft-reset pattern. The identified bit match triggers a soft reset which eliminates the need for an extra reset pin, when testing in scan mode.
Public/Granted literature
Information query
Patent Agency Ranking
0/0