Invention Grant
US07962829B2 Parity prediction circuit and logic operation circuit using same 失效
奇偶校验预测电路和逻辑运算电路使用相同

  • Patent Title: Parity prediction circuit and logic operation circuit using same
  • Patent Title (中): 奇偶校验预测电路和逻辑运算电路使用相同
  • Application No.: US11905307
    Application Date: 2007-09-28
  • Publication No.: US07962829B2
    Publication Date: 2011-06-14
  • Inventor: Hiroaki Atsumi
  • Applicant: Hiroaki Atsumi
  • Applicant Address: JP Kawasaki
  • Assignee: Fujitsu Limited
  • Current Assignee: Fujitsu Limited
  • Current Assignee Address: JP Kawasaki
  • Main IPC: H03M13/00
  • IPC: H03M13/00
Parity prediction circuit and logic operation circuit using same
Abstract:
In a parity prediction circuit which corrects the predicted parity using AND/OR parity inversion condition generation circuits, predicted parity and inversion conditions are corrected using an EOR condition of one of data buses. Two parity prediction logics are sufficient; the added correction logic circuit requires only the EOR condition for one data bus, and the hardware configuration can be reduced. Further, control signals from opcode signals are employed in the latter half of the logic operations, and thereby parity prediction is possible at high speed comparable with circuits which have parity prediction logic for each instruction.
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