Invention Grant
- Patent Title: Method for manufacturing semiconductor chip and method for processing semiconductor wafer
- Patent Title (中): 制造半导体芯片的方法和半导体晶片的处理方法
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Application No.: US12373813Application Date: 2007-08-24
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Publication No.: US07964449B2Publication Date: 2011-06-21
- Inventor: Hiroshi Haji , Kiyoshi Arita
- Applicant: Hiroshi Haji , Kiyoshi Arita
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Pearne & Gordon LLP
- Priority: JPP2006-227647 20060824
- International Application: PCT/JP2007/066960 WO 20070824
- International Announcement: WO2008/023849 WO 20080228
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
In a laser processing step S3, boundary sections among semiconductor elements 2 of a resist film 4 are exposed to a laser beam 13a, to thus form in the resist film 4 boundary grooves 5—which partition the semiconductor elements 2 from each other—and to uncover a surface 1b of a semiconductor wafer 1 in the boundary grooves 5. In a plasma etching step S6, the surface 1b of the semiconductor wafer 1 exposed in the boundary grooves 5 is etched by means of plasma Pf of a fluorine-based gas, to thus separate the semiconductor wafer 1 into individual semiconductor chips 1′ along the boundary grooves 5. Between the laser processing step S3 and the plasma etching step S6, there is performed processing pertaining to a boundary-groove-surface smoothing step S5 for smoothing, by means of plasma Po of oxygen gas, surfaces of the boundary grooves 5 having assumed an irregular shape in the laser processing step S3.
Public/Granted literature
- US20100055875A1 METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP AND METHOD FOR PROCESSING SEMICONDUCTOR WAFER Public/Granted day:2010-03-04
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