Invention Grant
- Patent Title: Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure
- Patent Title (中): 平面场效应晶体管结构具有倾斜的结晶刻蚀源极/漏极凹槽和形成晶体管结构的方法
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Application No.: US11873731Application Date: 2007-10-17
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Publication No.: US07964910B2Publication Date: 2011-06-21
- Inventor: Thomas W. Dyer
- Applicant: Thomas W. Dyer
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb I. P. Law Firm, LLC
- Agent Joseph Petrokaitis, Esq.
- Main IPC: H01L29/66
- IPC: H01L29/66
Abstract:
Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.
Public/Granted literature
- US20090101942A1 PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD Public/Granted day:2009-04-23
Information query
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