Invention Grant
- Patent Title: Compensation techniques for reducing power consumption in digital circuitry
- Patent Title (中): 用于降低数字电路功耗的补偿技术
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Application No.: US12160373Application Date: 2007-10-31
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Publication No.: US07965133B2Publication Date: 2011-06-21
- Inventor: Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
- Applicant: Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
- Applicant Address: US PA Allentown
- Assignee: Agere Systems Inc.
- Current Assignee: Agere Systems Inc.
- Current Assignee Address: US PA Allentown
- Agency: Ryan, Mason & Lewis, LLP
- International Application: PCT/US2007/083168 WO 20071031
- International Announcement: WO2009/058141 WO 20090507
- Main IPC: G05F1/10
- IPC: G05F1/10

Abstract:
A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.
Public/Granted literature
- US20100244937A1 Compensation Techniques for Reducing Power Consumption in Digital Circuitry Public/Granted day:2010-09-30
Information query
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