A digital phase detector is provided that can be easily implemented in gate array or FPGA, to accurately quantize a phase difference of two clocks and convert to a digital value without using delay elements. The digital phase detector includes: a multiplier for, when two clocks have frequencies close to an integer ratio, receiving a first clock and multiplying by M/N; F/F for latching a second clock by an output clock of the multiplier; a differential circuit for differentiating an output of the F/F; a counter for receiving the output clock of the multiplier; a latch circuit for holding an output of the counter according to an output of the differential circuit; a first adder for adding an output of the latch circuit; a second adder for subtracting an output of the first adder from a fixed value; and an accumulator for sequentially integrating an output of the second adder.