The clock data restoration device 1 is a device which restores a clock signal and data on the basis of an input digital signal and comprises an equalizer section 10, a sampler section 20, a clock generation section 30, an equalizer control section 40, and a phase monitor section 50. As a result of the loop processing of the equalizer section 10, the sampler section 20, and the equalizer control section 40, a control of a level adjustment amount of the digital signal by the equalizer section 10 is carried out. However, the control is stopped by the phase monitor section 50 when the phase difference between the clock signal CK and the digital signal is greater than a predetermined value. As a result, a clock signal and data can be restored more accurately.