A counter circuit adding a first value indicated by a plurality of bits and a second value in response to a clock signal, a first part of the plurality of bits being lower order than a second part of the plurality of bits, the counter circuit including a first counter configured to add the first part of the plurality of bits and the second value in response to the clock signal to output a third value regarding a result of adding the first and the second values, a second counter configured to add the second part of the plurality of bits and a fourth value in response to the clock signal, and a clock transmission control circuit coupled to the first and second counters to receive the clock signal and the third value, and to control whether or not to supply the clock signal to the second counter in accordance with the received third value.