Invention Grant
US07966455B2 Memory compression implementation in a multi-node server system with directly attached processor memory 有权
在具有直接连接的处理器存储器的多节点服务器系统中的内存压缩实现

Memory compression implementation in a multi-node server system with directly attached processor memory
Abstract:
A method, apparatus and program product enable scalable bandwidth and memory for a system having processor with directly attached memory. Multiple memory expander microchips provide the additional bandwidth and memory while in communication with the processor. Lower latency data may be stored in a memory expander microchip node in the most direct communication with the processor. Memory and bandwidth allocation between may be dynamically adjusted.
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