Invention Grant
- Patent Title: Configurable cache for a microprocessor
- Patent Title (中): 微处理器的可配置缓存
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Application No.: US11928322Application Date: 2007-10-30
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Publication No.: US07966457B2Publication Date: 2011-06-21
- Inventor: Rodney J. Pesavento , Gregg D. Lahti , Joseph W. Triece
- Applicant: Rodney J. Pesavento , Gregg D. Lahti , Joseph W. Triece
- Applicant Address: US AZ Chandler
- Assignee: Microchip Technology Incorporated
- Current Assignee: Microchip Technology Incorporated
- Current Assignee Address: US AZ Chandler
- Agency: King & Spalding L.L.P.
- Main IPC: G06F12/14
- IPC: G06F12/14

Abstract:
A cache module for a central processing unit has a cache control unit coupled with a memory, and a cache memory coupled with the control unit and the memory wherein the cache memory has a plurality of cache lines, each cache line having a storage area for storing instructions to be issued sequentially and associated control bits, wherein at least one cache line of the plurality of cache lines has at least one branch trail control bit which when set provides for an automatic locking function of the cache line in case a predefined branch instruction has been issued.
Public/Granted literature
- US20080147978A1 Configurable Cache for a Microprocessor Public/Granted day:2008-06-19
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