Invention Grant
US07966542B2 Method and apparatus for performing low-density parity-check (LDPC) code operations using a multi-level permutation 有权
用于使用多级置换执行低密度奇偶校验(LDPC)码操作的方法和装置

  • Patent Title: Method and apparatus for performing low-density parity-check (LDPC) code operations using a multi-level permutation
  • Patent Title (中): 用于使用多级置换执行低密度奇偶校验(LDPC)码操作的方法和装置
  • Application No.: US11674147
    Application Date: 2007-02-13
  • Publication No.: US07966542B2
    Publication Date: 2011-06-21
  • Inventor: Tom Richardson
  • Applicant: Tom Richardson
  • Applicant Address: US CA San Diego
  • Assignee: QUALCOMM Incorporated
  • Current Assignee: QUALCOMM Incorporated
  • Current Assignee Address: US CA San Diego
  • Agent Milan I. Patel
  • Main IPC: H03M13/00
  • IPC: H03M13/00
Method and apparatus for performing low-density parity-check (LDPC) code operations using a multi-level permutation
Abstract:
Methods and apparatus of the present invention are used to implement a communications system wherein different devices using the same LDPC code are implemented using different levels of parallelism. The use of a novel class of LDPC codes makes such differences in parallelism possible. Use of a factorable permuter in various embodiments of the invention make LDPC devices with different levels of parallelism in the encoder and decoder relatively easy to implement when using the codes in the class of LDPC codes discussed herein. The factorable permuter is implemented as a controllable multi-stage switching device which performs none, one, or multiple sequential reordering operations on a Z element vector passed between memory and a Z element vector processor, with the switching one individual vectors being controlled in accordance with the graph structure of the code being implemented.
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