The correction of errors in the transport and processing of qubits makes use of logical qubits made up of a plurality of physical qubits. The process takes place on a spatial array of physical qubit sites arranged with a quasi-2-dimensional topology having a first line of physical qubit sites and second line of physical qubit sites, where the first and second lines are arranged in parallel, with the sites of the first line in registration with corresponding sites in the second line. Between the first and second lines of physical qubit sites are a plurality of logic function gates, each comprised of a first physical qubit gate site associated with a first physical qubit site in the first line, and a second physical qubit gate site associated with the physical qubit site in the second line that corresponds to the first physical qubit site. The temporal process comprises a number of steps to achieve movement of the qubits in the array to bring pairs of all the data and ancilla qubits to respective logic function gates over the course of a number of clock cycles. Then achieve the logic operation between each pair of data and ancilla qubits. Move the qubits in the array to bring all the data and ancilla qubits to respective sites where they can be read out. And, using the values of the ancilla qubits read out to correct errors arising in the data qubits they have been gated with.