Invention Grant
US07966594B2 Automated method for the hierarchical and selective insertion of dummy surfaces into the physical design of a multilayer integrated circuit
有权
用于分层和选择性地将虚拟表面插入到多层集成电路的物理设计中的自动方法
- Patent Title: Automated method for the hierarchical and selective insertion of dummy surfaces into the physical design of a multilayer integrated circuit
- Patent Title (中): 用于分层和选择性地将虚拟表面插入到多层集成电路的物理设计中的自动方法
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Application No.: US12007678Application Date: 2008-01-14
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Publication No.: US07966594B2Publication Date: 2011-06-21
- Inventor: Marta Zorrilla , Vivian Blanchard
- Applicant: Marta Zorrilla , Vivian Blanchard
- Applicant Address: FR Les Clayes Sous Bois
- Assignee: Bull S.A.
- Current Assignee: Bull S.A.
- Current Assignee Address: FR Les Clayes Sous Bois
- Agency: Miles & Stockbridge P.C.
- Priority: FR0402011 20040227
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
The invention relates to an automated method for inserting dummy surfaces (95) into the various layers of the physical design (121) of multilayer integrated circuits organized in interconnected units (2) containing interconnected blocks (30) composed of interconnected cells (3), implemented by an integrated circuit design system (100). The multilayer integrated circuit design (121), stored in the design system (100) is implemented layer by layer, through selective insertion of patterns of dummy surfaces (95), the selective insertion is based on an insertion hierarchy that respects the hierarchy of the physical design (121) of the integrated circuits, by means of individual implementation of the interconnected blocks (30) and first interconnection routing (31) for said interconnected blocks (30) and individual implementation of the interconnected units (2) and second interconnection routing (22) for said interconnected units (2). The patterns of dummy surfaces are established selectively in accordance with the design of the blocks (30) of the integrated circuit.
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