Invention Grant
- Patent Title: Place-and-route layout method with same footprint cells
- Patent Title (中): 具有相同占位面积单元格的布局和布局方法
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Application No.: US12199617Application Date: 2008-08-27
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Publication No.: US07966596B2Publication Date: 2011-06-21
- Inventor: Lee-Chung Lu , Chung-Hsing Wang , Ping Chung Li , Chun-Hui Tai , Li-Chun Tien , Gwan Sin Chang
- Applicant: Lee-Chung Lu , Chung-Hsing Wang , Ping Chung Li , Chun-Hui Tai , Li-Chun Tien , Gwan Sin Chang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: K&L Gates LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F11/22
Abstract:
This invention discloses a method for automatically generating an integrated circuit (IC) layout, the method comprises determining a first cell height, creating a plurality of standard cells all having the first cell height, and generating the IC layout from the plurality of standard cells by placing and routing thereof.
Public/Granted literature
- US20100058267A1 PLACE-AND-ROUTE LAYOUT METHOD WITH SAME FOOTPRINT CELLS Public/Granted day:2010-03-04
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