Invention Grant
US07969016B2 Self-aligned wafer or chip structure, and self-aligned stacked structure
有权
自对准晶片或芯片结构,以及自对准堆叠结构
- Patent Title: Self-aligned wafer or chip structure, and self-aligned stacked structure
- Patent Title (中): 自对准晶片或芯片结构,以及自对准堆叠结构
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Application No.: US11946814Application Date: 2007-11-28
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Publication No.: US07969016B2Publication Date: 2011-06-28
- Inventor: Jung-Tai Chen , Tzong-Che Ho , Chun-Hsun Chu
- Applicant: Jung-Tai Chen , Tzong-Che Ho , Chun-Hsun Chu
- Applicant Address: TW Hsinchu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Priority: TW96122443A 20070622
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A self-aligned wafer or chip structure including a substrate, at least one first concave base, at least one second concave base, at least one connecting structure and at least one bump is provided. The substrate has a first surface and a second surface, and at least one pad is formed on the first surface. The first concave base is disposed on the first surface and electrically connected to the pad. The second concave base is disposed on the second surface. The connecting structure passes through the substrate and disposed between the first and second concave bases so as to be electrically connected to the first and second concave bases. The bump is filled in the second concave base and protrudes out of the second surface.
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