Invention Grant
US07969174B2 Systems and methods for test time outlier detection and correction in integrated circuit testing
有权
集成电路测试中测试时间异常值检测和校正的系统和方法
- Patent Title: Systems and methods for test time outlier detection and correction in integrated circuit testing
- Patent Title (中): 集成电路测试中测试时间异常值检测和校正的系统和方法
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Application No.: US12418024Application Date: 2009-04-03
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Publication No.: US07969174B2Publication Date: 2011-06-28
- Inventor: Gil Balog , Reed Linde , Avi Golan
- Applicant: Gil Balog , Reed Linde , Avi Golan
- Applicant Address: IL
- Assignee: OptimalTest Ltd.
- Current Assignee: OptimalTest Ltd.
- Current Assignee Address: IL
- Agency: Occhiuti Rohlicek & Tsao LLP
- Main IPC: G01R31/26
- IPC: G01R31/26
Abstract:
Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
Public/Granted literature
- US20090192754A1 SYSTEMS AND METHODS FOR TEST TIME OUTLIER DETECTION AND CORRECTION IN INTEGRATED CIRCUIT TESTING Public/Granted day:2009-07-30
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