Invention Grant
- Patent Title: Decoder circuit
- Patent Title (中): 解码电路
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Application No.: US12700023Application Date: 2010-02-04
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Publication No.: US07969201B2Publication Date: 2011-06-28
- Inventor: Tomohiro Hanyu
- Applicant: Tomohiro Hanyu
- Applicant Address: JP Tokyo
- Assignee: Oki Semiconductor Co., Ltd.
- Current Assignee: Oki Semiconductor Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Volentine & Whitt, PLLC
- Priority: JP2009-030044 20090212
- Main IPC: G11C8/00
- IPC: G11C8/00 ; G09G3/36

Abstract:
A decoder circuit that can prevent the delay of decoder output includes a switch that is put into an ON state when a node A of an NMOS region is not an output channel of a selected gradation voltage. The switch is connected to the node A. Thus, a voltage raised by electric charges accumulated by a coupling capacity C1 caused in the node A when the gradation voltage is outputted from an output terminal of the decoder output can be discharged by the switch in the ON state.
Public/Granted literature
- US20100201401A1 DECODER CIRCUIT Public/Granted day:2010-08-12
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