Invention Grant
- Patent Title: Circuit to reduce duty cycle distortion
- Patent Title (中): 电路减少占空比失真
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Application No.: US12486579Application Date: 2009-06-17
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Publication No.: US07969224B2Publication Date: 2011-06-28
- Inventor: Paul M. Werking
- Applicant: Paul M. Werking
- Applicant Address: US NJ Morristown
- Assignee: Honeywell International, Inc.
- Current Assignee: Honeywell International, Inc.
- Current Assignee Address: US NJ Morristown
- Agency: Shumaker & Sieffert, P.A.
- Main IPC: H03K17/62
- IPC: H03K17/62

Abstract:
A method and a circuit for correcting duty cycle distortion. A delay insertion gate corrects data dependent delay distortion that is generated by CMOS flip-flop circuits. The delay insertion gate includes two field effect transistors and a current mirror. The two transistors each respectively receive an input signal from an upstream circuit. At least one of the transistors is coupled to an output node. The output node temporarily holds a voltage state within the delay insertion gate, correcting any distortion in the duty cycle of the input signals.
Public/Granted literature
- US20090322396A1 CIRCUIT TO REDUCE DUTY CYCLE DISTORTION Public/Granted day:2009-12-31
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