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US07970998B2 Parallel caches operating in exclusive address ranges 有权
在独占地址范围内运行的并行缓存

Parallel caches operating in exclusive address ranges
Abstract:
A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.
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