Invention Grant
- Patent Title: Parallel caches operating in exclusive address ranges
- Patent Title (中): 在独占地址范围内运行的并行缓存
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Application No.: US11910831Application Date: 2006-03-17
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Publication No.: US07970998B2Publication Date: 2011-06-28
- Inventor: Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
- Applicant: Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Greenblum & Bernstein, P.L.C.
- Priority: JP2005-112840 20050408
- International Application: PCT/JP2006/305389 WO 20060317
- International Announcement: WO2006/109421 WO 20061019
- Main IPC: G06F12/08
- IPC: G06F12/08

Abstract:
A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.
Public/Granted literature
- US20090077318A1 CACHE MEMORY Public/Granted day:2009-03-19
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