A device that includes an error detection circuit that is configured to detect a timing error resulting from a fast voltage drop by comparing a signal from a critical path to a signal from a replica path; and a clock signal provider that is adapted to receive a clock signal and to delay, by a fraction of the clock cycle and in response to a detection of the timing error, the clock signal to provide a delayed clock signal that is provided to a clocked circuit that is coupled to the critical path; and a controller that is configured determine a level of a supply voltage in response to a capability of the error detection circuit and the clock signal provider to manage fast voltage drops; wherein the supply voltage is provided to at least one component of the critical path.