Invention Grant
- Patent Title: Assessing resources required to complete a VLSI design
- Patent Title (中): 评估完成VLSI设计所需的资源
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Application No.: US12100481Application Date: 2008-04-10
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Publication No.: US07971164B2Publication Date: 2011-06-28
- Inventor: Derick G. Behrends , Travis R. Hebig , Daniel M. Nelson , Jesse D. Smith
- Applicant: Derick G. Behrends , Travis R. Hebig , Daniel M. Nelson , Jesse D. Smith
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Toler Law Group
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A system, method and program product are described in which schematics in a library that a user has tagged are read as ready for layout. The difficulty of each layout is assessed based on statistics indicative of the complexity of the schematic. The statistics may regard the number of connections, pins, devices, and other schematic information. The information is used to calculate the total amount of effort required to complete the design and generate a report.
Public/Granted literature
- US20090259977A1 Assessing Resources Required to Complete a VLSI Design Public/Granted day:2009-10-15
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